A conventional method of combining a semiconductor chip with a substrate is such that spacers for controlling space are provided on either the semiconductor chip or the substrate, for keeping a space between a device-formed surface of the semiconductor chip and a circuit-formed surface of the substrate constant.
For instance, as FIG. 8 illustrates, Japanese Laid-Open Patent Application No. 7-249632/1995 (Tokukaihei 7-249632; published on Sep. 26, 1995; conventional art (A)) discloses a semiconductor device in which core parts 102 are used for the spacers to keep a space between a device-formed surface of a semiconductor chip 100 and a circuit-formed surface of a substrate 101 constant.
Between the semiconductor chip 100 and the substrate 101, the core parts 102, solder bumps 103, and external electrode pads 104 are provided. The core parts 102, which are made of metal and have a melting point higher than that of the solder bumps 103, are attached to the external electrode pad 104 using solder (not illustrated).
In the case of flip chip mounting, the core parts 102 are bonded on the external electrode pads 104 on the semiconductor chip 100 using solder which is not illustrated and has a melting point higher than that of the solder bumps 103, and the semiconductor chip 100 is connected to the solder bumps 103 formed on the external electrode pads 104 on the substrate 101.
Moreover, for instance, as illustrated in FIG. 9, Japanese Laid-Open Patent Application No. 10-154726/1998 (Tokukaihei 10-154726; published on Jun. 9, 1998; conventional art (B)) discloses a semiconductor device in which gold bumps 112, which have a melting point higher than that of the solder bumps 113 which are for combining the semiconductor chip 110 with the substrate 111, are used as the spacers.
On the semiconductor chip 110, dummy electrode pads 114 which are electrically isolated from predetermined conductive parts on the semiconductor chip 110 and external electrode pads 115 which are electrically connected to the conductive parts on the semiconductor chip 110 are provided. Likewise, the dummy electrodes 114 and the external electrode pads 115 are also provided on the substrate 111.
The external electrode pads 115 on the substrate 111 and the external electrode pads 115 on the semiconductor chip 110 are provided so as to face each other via the solder bumps 113, and thus these two sets of the electrode pads are electrically connected. Also, the dummy electrode pads 114 on the substrate 111 and the dummy electrode pads 114 on the semiconductor chip 110 are provided so as to face each other via the gold bumps 112. It is thus possible to keep a predetermined space between the substrate 111 and the semiconductor chip 110.
Furthermore, for instance, as illustrated in FIG. 10, Japanese Laid-Open Patent Application No. 11-40716/1999 (Tokukaihei 11-40716; published on Feb. 12, 1999; conventional art (C)) discloses a semiconductor device in which the space is kept to be constant using conductive particles 122 as the spacers.
As the figure shows, the semiconductor device is arranged such that the conductive particles 122 are interfused in an electrode combining solder 123. In this manner, it is possible to keep the space between a substrate 121 and a metal base 120 constant at a diameter of the conductive particles 122.
Furthermore, Japanese Laid-Open Patent Application No. 7-221104/1995 (Tokukaihei 7-221104; published on Aug. 18, 1995; conventional art (D)) discloses a semiconductor device which is provided with electrode pins each having identical height. The electrode pins are formed on the external electrode pads of the semiconductor chip, by forming conductive combining material (thermosetting resin mixed with metal particles) by a printing method so as to thermoset the same. Then the semiconductor chip and the substrate are combined with each other by a method such that a solder is provided on a tip of each of the electrode pins and then the electrode pins are provided downward toward the substrate so as to be heated. In this manner, this semiconductor device is arranged so that the electrode pins are used as the spacers and the semiconductor chip is combined with the substrate using solder.
However, the above-identified constitutions have problems as described below.
The constitution disclosed in the conventional art (A) is arranged so that the core parts 102 are connected to the external electrode pads 104 using the solder which is not illustrated. Thus, when manufacturing the semiconductor device, this constitution requires the steps of: forming solder paste, which is for connecting the core parts 102 to the external electrode pads 104, on the external electrode pads 104 on the semiconductor chip 100 by printing, etc.; mounting the core parts 102 on the solder paste formed on the external electrode pads 104; and connecting the external electrode pads 104 to the core parts 102 by reflow-soldering the solder paste. Consequently, a number of manufacturing steps are required so that there is a limit to reduce the cycle time.
The constitution disclosed in the conventional art (B) includes the gold bumps 112 for keeping the space and the solder bumps 113 for combining. Thus this constitution requires either: forming the gold bumps 112 and the solder bumps 113 through wire bonding; or forming the gold bumps 112 through wire bonding whereas forming the solder bumps 113 through solder plating. Thus a number of manufacturing steps are required so that there is a limit to reduce the cycle time.
The constitution disclosed in the conventional art (C) is arranged so that the electrode connecting solder 123, in which the conductive particles 122 are interfused, is formed on the metal base 120 by a method such as printing using a stencil plate and discharging from a dispense nozzle. In this constitution, the diameter of the conductive particles 122 must be smaller than (i) a circle inscribing the diameter of the smallest opening in a pattern formed on the stencil plate or (ii) the diameter of the dispense nozzle.
Generally, for instance, when the space between a plurality of combined semiconductor chips or the space between the semiconductor chip and the wiring substrate being combined with each other is filled with liquid resin for improving the reliability of the semiconductor device, the thickness of the space is an important factor of determining the state of the filled liquid resin.
However, it is difficult to make the space between the plurality of semiconductor chips or between the semiconductor chip and the wiring substrate not narrower than the diameter of the circle inscribing the smallest opening in the pattern formed on the stencil printing plate or the diameter of the dispense nozzle, i.e. not narrower than the diameter of a circle inscribing the facing external electrode pads.
More specifically, in the case of the constitution disclosed in the conventional art (C), it is difficult to make the space between the metal base 120 and the substrate 121 not narrower than the diameter of the circle inscribing the smallest opening in the pattern formed on the stencil plate or the diameter of the dispense nozzle.
Moreover, the constitutions disclosed in conventional arts (A), (B), (C), and (D) use solder to combine the semiconductor chip with the substrate. In these cases, generally flux is provided on the combining surface so that a step for removing the flux is required after the combining. This brings about the increase of the number of manufacturing steps and hence there is a limit to reduce the cycle time.
Furthermore, the combining process using solder requires a temperature around 260° C. Thus, when the post-thermoset thermosetting resin is adopted as in the constitution disclosed in the conventional art (D), the thermosetting resin could be degraded or deformed on the occasion of the combining process using solder.
As described above, using solder for combining the plurality of semiconductor chips with each other or combining the semiconductor chip with the substrate gives rise to the increase of the manufacturing steps and requires high temperature for the combining since the melting point of solder is high. Moreover, when particles are utilized as the spacers and the thickness of the space is determined by the diameter of the particles, there is a limit to the thickness of the space between the plurality of semiconductor chips or between the semiconductor chip and the wiring substrate.